ADZS-21371-EZLITE【PDF 13/56 页】KIT EVAL EZLITE ADZS-21371

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ADSP-21371 / ADSP-21375

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 9 :

A = asynchronous, I = input, O = output, S = synchronous,

(A/D) = active drive, (O/D) = open drain, and T = three-state,

(pd) = pull-down resistor, (pu) = pull-up resistor.

Table 9. Pin Descriptions

State During

and After

Name

ADDR 23–0

DATA 31–0

Type

O/T (pu)

I/O (pu)

Reset

Pulled high/

driven low

Pulled high/

pulled high

Description

External Address. The processor outputs addresses for external memory and periph-

erals on these pins.

External Data. The data pins can be multiplexed to support the external memory

interface data (I/O), the PDAP (I) (PDAP for ADSP-21371), FLAGS (I/O) and PWM (O). After

reset, all DATA pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode (default).

When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the external port

data pins for parallel input data. PDAP over 16-bit external port DATA is not supported

on the ADSP-21375 processor.

DAI _P 20–1

I/O with

programmable

(pu) 1

Pulled high/

pulled high

Digital Applications Interface Pins . These pins provide the physical interface to the

DAI SRU. The DAI SRU configuration registers define the combination of on-chip audio-

centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.

The configuration registers of these peripherals then determine the exact behavior of

the pin. Any input or output signal present in the DAI SRU may be routed to any of these

pins. The DAI SRU provides the connection from the serial ports, the S/PDIF module

(ADSP-21371), IDP (2), and the PCGs (4), to the DAI_P20–1 pins. Pullups can be disabled

via the DAI_PIN_PULLUP register.

DPI _P 14–1

I/O with

programmable

(pu) 1

Pulled high/

pulled high

Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.

The DPI SRU configuration registers define the combination of on-chip peripheral inputs

or outputs connected to the pin and to the pin’s output enable. The configuration

registers of these peripherals then determines the exact behavior of the pin. Any input

or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU

provides the connection from the timers (2), SPIs (2), UART (1), flags (12), and general-

purpose I/O (9) to the DPI_P14–1 pins. Pull-ups can be disabled via the DPI_PIN_PULLUP

register.

ACK

I (pu)

Memory Acknowledge. External devices can deassert ACK (low) to add wait states to

an external memory access. ACK is used by I/O devices, memory controllers, or other

peripherals to hold off completion of an external memory access.

RD

WR

SDRAS

SDCAS

SDWE

O/T (pu)

O/T (pu)

O/T (pu)

O/T (pu)

O/T (pu)

Pulled high/

driven high

Pulled high/

driven high

Pulled high/

driven high

Pulled high/

driven high

Pulled high/

External Port Read Enable. RD is asserted whenever the processor reads a word from

external memory. RD has a 22.5 k ? internal pull-up resistor.

External Port Write Enable. WR is asserted when the processor writes a word to

external memory. WR has a 22.5 k ? internal pull-up resistor.

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

SDRAM Column Address Select. Connect to SDRAM's CAS pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

driven high

Rev. D | Page 13 of 56 | April 2013

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